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Title
    Formal Verification Engineer
Description:

    NeuroBlade is looking for a Formal Verification Engineer to join our fast-growing engineering team. We are looking for brilliant and passionate people to join us and play a major role in building the next big thing in AI! If you enjoy working on cutting edge technologies and solving complex problems, and have team spirit and a can-do-attitude – Your place is with us!

    Founded in 2017, NeuroBlade set out on a mission to redefine computer architecture for AI and other memory intensive tasks. We build high performance solutions for the rapidly growing AI market while lowering costs and power usage. NeuroBlade’s unique hardware solution paired with a complete end-to-end SW stack, enables businesses to take the next leap forward by increasing the efficiency and affordability of their devices from edge devices to data centers.

Responsibilities
  • Design, review and deploy formal verification environments using Jasper or similar tools
  • Verify the design and hunt for bugs
  • Use state of the art verification tools and technologies
Requirements
  • Deep understanding and proven experience in formal verification using Jasper or similar tools
  • Experience in writing SVA assertions
  • Scripting knowledge – perl, python, TCL, etc.
  • Electronics Engineering degree from a leading institution, graduated with honor
Nice to have:
  • Knowledge of AI/ML
  • Knowledge and experience in VLSI verification flow, languages & concepts
  • Experience in verification environments using SystemVerilog UVM
  • Experience in logic design, circuit design, and full chip integration

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